1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and in particular to a resistance reduction process for a semiconductor device such as a DRAM device.
2. Description of the Related Art
In order to speed up a logic device or a device having DRAM and a logic circuit incorporated therein, it is necessary to reduce the resistance by a silicide process at the connection points where metal wiring is connected to a source electrode, drain electrode, gate electrode, and polysilicon contact. For this purpose, a cobalt silicide technology is typically utilized from the viewpoint of a wiring thinning effect or heat resistance (e.g. Japanese Laid-Open Patent Publication No. 2002-75905 (Patent Document 1)).
According to Patent Document 1, formation of cobalt silicide is achieved by depositing cobalt on source and drain regions, which are exposed from an insulating film selectively formed on a semiconductor substrate, on a silicon gate electrode formed over a portion of the semiconductor substrate, and on the insulating film, and then forming a cobalt silicide film by heat treatment on the source and drain regions and the silicon gate electrode. Any cobalt remaining unreacted is removed by an etchant consisting of aqueous solution of mixture of hydrochloric acid, hydrogen peroxide and water. Source and drain electrodes and gate electrode are thus formed with their resistance reduced in a self-alignment manner.
On the other hand, for the purpose of reducing the resistance of a gate electrode, it has become mainstream to utilize a gate electrode having a polymetal structure (polymetal gate) in which a metal film having a high melting point and low resistance is stacked on a polysilicon film. In particular, the use of a tungsten polymetal gate formed of a tungsten film is becoming mainstream. Since tungsten is dissolved by a chemical solution having hydrogen peroxide solution mixed therein, the silicide process cannot be performed by using the tungsten polymetal gate in the method as described in Patent Document 1. Accordingly, APM solution (mixture of ammonia water, hydrogen peroxide solution and water, “APM” standing for ammonium hydroxide-hydrogen peroxide-mixture) or SPM solution (mixture of sulfuric acid, hydrogen peroxide solution and water, “SPM” standing for sulfuric acid-hydrogen peroxide-mixture) which is normally used in a cleaning process for a semiconductor device cannot be used in a state where the tungsten polymetal gate is exposed. Therefore, an additional process is required to protect the tungsten gate wiring before performing the silicide process, resulting in increase of the number of photolithography steps.
These problems will be described with reference to FIG. 1 which is a cross-sectional view showing part of a cell formation region (the left side) and a peripheral circuit formation region (right side) in a DRAM device fabricating process. Although in the cell formation region, another region is formed on the left of the leftmost line, symmetrical to the region indicated on the right of the leftmost line, this symmetrical region is omitted from FIG. 1. FIG. 1 shows a state in which a first opening 41 and a second opening 43 are formed in a laminated structure having various types of films and a gate electrode formed over a substrate. Processes to form such a structure will be described so far as the present invention is concerned. A substrate 10 has an element isolation region 11 formed of an oxide film, an active region (not shown) and so on. There are formed on this substrate 11, a gate insulating film (silicon oxide film) (not shown), a polysilicon film, a tungsten nitride film (not shown), a tungsten film, and a silicon nitride film. A resist pattern (not shown) is formed in a predetermined region where a gate electrode is to be formed. Using this resist pattern as a mask, the silicon nitride film is etched to form a gate cap 23. After removing the resist pattern, the gate cap 23 is used as a mask to etch away the tungsten film and the tungsten nitride film, and to form a tungsten polymetal gate composed of a tungsten film 22, a tungsten nitride film (not shown), and a polysilicon gate 21.
Subsequently, a silicon nitride film is formed and anisotropically etched back to form gate side wall 24. Photolithography process and ion implantation are then performed to form an N+ diffusion layer or a P+ diffusion layer in the substrate, and a source region and a drain region are formed. Further, an oxide film 35 to be a first interlayer insulating film is formed on the entire surface, and then a contact hole is formed therein. The contact hole is filled with polysilicon, forming a contact plug 32. Subsequently, a second interlayer insulating film 37 is stacked thereon. A first opening (first contact hole) 41 and second opening (second contact hole) 43 are formed through the second interlayer insulating film. The first opening (first contact hole) 41 has such a depth that the top face of the contact plug 32 is exposed. The second opening (second contact hole) 43 extends also through the first interlayer insulating film, having such a depth as to reach the substrate in the peripheral circuit formation region. FIG. 1 shows a structure obtained by the method as described above.
In a state in which the first opening 41 and the second opening 43 are formed as shown in FIG. 1, a cobalt film 51 is formed by sputtering as shown in FIG. 2.
The structure is then thermally treated in an inert gas atmosphere at a temperature of 500° C. or higher to form a cobalt silicide layer 52 on the surface of the contact plug 32 in the first opening 41 and on the surface of the substrate 10 in the second opening 43, as shown in FIG. 3.
Subsequently, any unreacted cobalt which has been left unsilicidized on the interlayer insulating film or the like is removed. According to the related art, the removal of the cobalt is performed by using SPM (mixed solution of sulfuric acid and hydrogen peroxide) or other chemical solutions having hydrogen peroxide solution mixed therein, so that a structure having a silicidized cobalt film as shown in FIG. 4 is obtained.
FIG. 4 shows a structure in which the surface of the contact plug and a region where wiring on the semiconductor substrate is connected are silicidized. A resist pattern (not shown) is formed and the oxide film 37 and the oxide film 35 are dry etched by using the resist pattern as a mask. Further, the nitride film forming the cap layer and another nitride film thereon are etched, whereby a contact hole 42 is formed to reach the tungsten polymetal gate (21, 22) in the peripheral circuit formation region. FIG. 5 shows the state in which the contact hole 42 has been formed in this manner.
In the state shown in FIG. 5, therefore, the first contact hole is formed through the second interlayer insulating film 37, and a silicide film 52 is formed on the contact plug 32 in the bottom of the first contact hole. A second contact hole is formed through the first interlayer insulating film 35 and the second interlayer insulating film 37, and a silicide film 52 is formed on the surface of the semiconductor substrate in the bottom of the second contact hole. A third contact hole is formed through the second interlayer insulating film 37 and the first interlayer insulating film 35 in the peripheral circuit formation region to such a depth as to reach the tungsten film of the tungsten polymetal gate.
Subsequently, a metal film (tungsten) for forming wiring is formed in the holes of the structure shown in FIG. 5 by a CVD process. After polishing off any excessive tungsten by a CMP process, a metal film (tungsten) for forming wiring is formed. As a result, as shown in FIG. 6, a contact 63 is formed in each of the first, second and third contact holes while, at the same time, a metal film 64 is formed on the entire surface. The metal wiring is then patterned to form wiring. Additionally, a cell storage capacitor and so on are formed.